Desired Skills & Experience Education: BSc in Electronic engineer from one of the leading universities. Experience: • 1-3 years of experience in team lead. • Min 4 years of experience in full flow of physical implementation (from RTL to GDSII) • Experience in Static Timing Analysis (Prime-Time and Prime Time SI) • Experience in Floor Plan, CTS, Place & Route, layout, and layout verification. • Proven experience with one of the Place& Route tools and flows (Synopsys, Magma or Cadence). • In-depth scripting and programming experience of the following: Perl, TCL, CSH /TCSH • Knowledge in Verilog/VHDL – advantage Relevant CV can be sent to

jobme336@gmail.com